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71M6521DE/DH/FE Data Sheet
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers ( TMOD and TCON )
are used to select the appropriate mode.
Timer/Counter Mode Control register ( TMOD ):
MSB
LSB
GATE
C/T
M1
M0
GATE
C/T
M1
M0
Timer 1
Timer 0
Table 21: The TMOD Register
Bits TR1 ( TCON.6 ) and TR0 ( TCON .4) in the TCON register (see Table 19 and Table 20) start their associated timers
when set.
Bit
TMOD.7
TMOD.3
TMOD.6
TMOD.2
TMOD.5
TMOD.1
TMOD.4
TMOD.0
Symbol
Gate
C/T
M1
M0
Function
If set, enables external gate control (pin int0 or int1 for Counter 0 or 1,
respectively). When int0 or int1 is high, and TRX bit is set (see TCON register), a
counter is incremented every falling edge on t0 or t1 input pin
Selects Timer or Counter operation. When set to 1, a Counter operation is
performed. When cleared to 0, the corresponding register will function as a Timer.
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD
description.
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD
description.
Table 22: TMOD Register Bit Description
M1
0
0
1
1
M0
0
1
0
1
Mode
Mode 0
Mode 1
Mode 2
Mode 3
Function
13-bit Counter/Timer with 5 lower bits in the TL0 or TL1 register and the
remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer 1,
respectively). The 3 high order bits of TL0 and TL1 are held at zero.
16-bit Counter/Timer.
8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1 ,
while TL0 or TL1 is incremented every machine cycle. When TL (x) overflows,
a value from TH (x) is copied to TL (x).
If Timer 1 M1 and M0 bits are set to '1', Timer 1 stops. If Timer 0 M1 and M0
bits are set to '1', Timer 0 acts as two independent 8-bit Timer/Counters.
Table 23: Timers/Counters Mode Description
Rev 3
Note:
In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 flag on overflow, while
TH0 is affected by the TR1 bit, and the TF1 flag is set on overflow.
Page: 27 of 107
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